A Flexible Embedding-Aware Near Memory Processing Architecture for Recommendation System

IF 1.4 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Lingfei Lu;Yudi Qiu;Shiyan Yi;Yibo Fan
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引用次数: 0

Abstract

Personalized recommendation system (RS) is widely used in the industrial community and occupies much time in AI computing centers. A critical component of RS is the embedding layer, which consists of sparse embedding lookups and is memory-bounded. Recent works have proposed near-memory processing (NMP) architectures to utilize high inner-memory bandwidth to speed up embedding lookups. These NMP works divide embedding vectors either horizontally or vertically. However, the effectiveness of horizontal or vertical partitioning is hard to guarantee under different memory configurations or embedding vector sizes. To improve this issue, we propose FeaNMP, a f lexible e mbedding- a ware NMP architecture that accelerates the inference phase of RS. We explore different partitioning strategies in detail and design a flexible way to select optimal ones depending on different embedding dimensions and DDR configurations. As a result, compared to the state-of-the-art rank-level NMP work RecNMP, our work achieves up to 11.1× speedup for embedding layers under mix-dimensioned workloads.
一种灵活的基于嵌入感知的推荐系统近记忆处理架构
个性化推荐系统(RS)广泛应用于工业领域,在人工智能计算中心占用了大量时间。RS的一个关键组成部分是嵌入层,它由稀疏嵌入查找组成,并且是有内存限制的。最近的工作提出了近内存处理(NMP)架构,以利用高内存带宽来加快嵌入查找。这些NMP作品可以水平或垂直地划分嵌入向量。然而,在不同的内存配置或嵌入向量大小下,很难保证水平或垂直分区的有效性。为了改善这个问题,我们提出了FeaNMP,一个灵活的嵌入-一个加速RS推理阶段的软件NMP架构,我们详细探讨了不同的划分策略,并设计了一种灵活的方法来选择最优的方法,这取决于不同的嵌入维数和DDR配置。因此,与最先进的秩级NMP工作RecNMP相比,我们的工作在混合维工作负载下实现了高达11.1倍的嵌入层加速。
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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