Charge Trap Flash structure with Feedback Field Effect Transistor for Processing in Memory

Abstract

Recently, a memory wall has become a concern due to the increasing distance between memory and CPU in the von Neumann structure. While the CPU and logic devices operate quickly, their speed becomes irrelevant due to the slow data transfer between them. Consequently, addressing the data delay problem between the CPU and the logic elements is crucial. To tackle this issue, researchers have been exploring the Processing in Memory (PIM) technology, which enables simultaneous memory and computation. However, traditional volatile or nonvolatile memory-based PIM approaches have inherent limitations in overcoming the memory wall problem, as memory and computation are performed sequentially on separate devices. Therefore, there is a need to develop a new memory-logic device capable of performing read and operation simultaneously. In this paper, we propose a Feedback Field Effect Transistor (FBFET) with a charge trap layer that can fulfill both memory and computational roles, thus implementing an ideal Processing in Memory technology. The device features an oxide-nitride-oxide structure, where nitride is coupled to the oxide side of the FBFET. It accumulates electric charges in the floating body for memory operations and reads the data stored in the charge trap layer for logic operations. By selecting the control gate bias, the computing operation can be configured to perform AND or OR operations. This enables simultaneous memory and logical operations to take place.