A hierarchical model-based method for wafer level virtual metrology under process information deficiency

Abstract

Online inspection is one of the most critical processes of quality control in semiconductor manufacturing. The physical inspection methods for wafers are time-consuming and unable to achieve wafer level metrology. In order to improve production efficiency and expand inspection coverage, virtual metrology (VM) methods have recently received widespread attention; they utilize process parameters to estimate wafer metrology results. However, due to process drift and other reasons, the process information contained in real-time signal data (RTS data) used for VM modeling in industrial production is insufficient. This work proposed a hierarchical modeling method for machine learning-based virtual wafer metrology, leveraging RTS and post-process quality characteristics. The hierarchical model consists of an multiway principle analysis (MPCA) sub-model for RTS feature extracting and two separate long short-term memory (LSTM) networks for wafer-to-wafer dynamics in RTS and quality characteristics, respectively. A case study on the thickness VM of chemical vapor deposition thin film is conducted, and the proposed method has achieved better results than other methods in comparison.