{"title":"A compact adderless feed-forward incremental \\(\\varDelta \\varSigma \\) with multiple global references for CMOS image sensors","authors":"Nicolas Callens, Georges Gielen","doi":"10.1007/s10470-023-02186-4","DOIUrl":null,"url":null,"abstract":"<div><p>This paper presents an adderless feed-forward incremental <span>\\(\\varDelta \\varSigma \\)</span> (I<span>\\(\\varDelta \\varSigma \\)</span>) with asynchronous SAR (ASAR) that removes the need for in-column calibration by using global references, eliminates an additional summing amplifier and reduces the conversion time by using a multi-bit ASAR quantizer. The proposed I<span>\\(\\varDelta \\varSigma \\)</span> ADC is designed in 40 nm CMOS technology and is laid out compactly in a 5 <span>\\(\\upmu \\)</span>m × 466 <span>\\(\\upmu \\)</span>m column. According to post-layout simulations, the ADC achieves an input-referred noise of 85 <span>\\(\\upmu \\)</span>V<span>\\(_{ rms }\\)</span>, a conversion time of 3.2 <span>\\(\\upmu \\)</span>s (with DCDS) and a power consumption of 230 <span>\\(\\upmu \\)</span>W. This results in a Walden FoM<span>\\(_{\\textrm{W}}\\)</span> of 234 fJ/conv.step and a FoM<span>\\(_{\\textrm{A}}\\)</span> = FoM<span>\\(_{\\textrm{W}} \\times \\text {A}_{\\text {ADC}}\\)</span> of 0.54 fJ<span>\\(\\cdot \\)</span>mm<span>\\(^2\\)</span>/conv.step, which demonstrates the feasibility of using the proposed architecture in CMOS image sensors.\n</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":null,"pages":null},"PeriodicalIF":1.2000,"publicationDate":"2023-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Analog Integrated Circuits and Signal Processing","FirstCategoryId":"5","ListUrlMain":"https://link.springer.com/article/10.1007/s10470-023-02186-4","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
This paper presents an adderless feed-forward incremental \(\varDelta \varSigma \) (I\(\varDelta \varSigma \)) with asynchronous SAR (ASAR) that removes the need for in-column calibration by using global references, eliminates an additional summing amplifier and reduces the conversion time by using a multi-bit ASAR quantizer. The proposed I\(\varDelta \varSigma \) ADC is designed in 40 nm CMOS technology and is laid out compactly in a 5 \(\upmu \)m × 466 \(\upmu \)m column. According to post-layout simulations, the ADC achieves an input-referred noise of 85 \(\upmu \)V\(_{ rms }\), a conversion time of 3.2 \(\upmu \)s (with DCDS) and a power consumption of 230 \(\upmu \)W. This results in a Walden FoM\(_{\textrm{W}}\) of 234 fJ/conv.step and a FoM\(_{\textrm{A}}\) = FoM\(_{\textrm{W}} \times \text {A}_{\text {ADC}}\) of 0.54 fJ\(\cdot \)mm\(^2\)/conv.step, which demonstrates the feasibility of using the proposed architecture in CMOS image sensors.
期刊介绍:
Analog Integrated Circuits and Signal Processing is an archival peer reviewed journal dedicated to the design and application of analog, radio frequency (RF), and mixed signal integrated circuits (ICs) as well as signal processing circuits and systems. It features both new research results and tutorial views and reflects the large volume of cutting-edge research activity in the worldwide field today.
A partial list of topics includes analog and mixed signal interface circuits and systems; analog and RFIC design; data converters; active-RC, switched-capacitor, and continuous-time integrated filters; mixed analog/digital VLSI systems; wireless radio transceivers; clock and data recovery circuits; and high speed optoelectronic circuits and systems.