Zhen-Jie Hong, Yu-Lung Lo, Kuan-Yu Shen, Guan-Yu Chen, Wei-Ju Li
{"title":"A wide-range and fast-locking all-digital DLL with one-cycle dynamic synchronizing for in-cell touched LC display","authors":"Zhen-Jie Hong, Yu-Lung Lo, Kuan-Yu Shen, Guan-Yu Chen, Wei-Ju Li","doi":"10.1007/s10470-023-02192-6","DOIUrl":null,"url":null,"abstract":"<div><p>This paper proposes wide-range and fast locking all-digital delay-locked loop (WRADDLL) circuit with one cycle dynamic synchronizing. The WRADDLL not only synchronizes the input and output clocks in 5 clock cycles but maintains one cycle dynamic locking. The WRADDLL reduces the clock skew between the input and output clocks with three innovative techniques. First, by improving the mirror control circuit, the WRADDLL operates correctly with a flexible duty cycle clock signal. Second, the WRADDLL works precisely and ignores the effect of output load changes by moving the measurement delay line beyond the output driver. Besides, it can achieve one-cycle dynamic locking. Finally, the WRADDLL utilizes the band selector to achieve wide-range operation. After fine tuning, the maximum static phase error is less than 3% of clock cycle. The chip is fabricated by 90 nm standard CMOS process. Its operating frequency range is from 200 MHz to 2 GHz. The power consumption and RMS jitter are 3.24 mW and 1.49 ps at 2 GHz, respectively. The active area of this chip is 0.011 mm<sup>2</sup>.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":null,"pages":null},"PeriodicalIF":1.2000,"publicationDate":"2023-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Analog Integrated Circuits and Signal Processing","FirstCategoryId":"5","ListUrlMain":"https://link.springer.com/article/10.1007/s10470-023-02192-6","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
This paper proposes wide-range and fast locking all-digital delay-locked loop (WRADDLL) circuit with one cycle dynamic synchronizing. The WRADDLL not only synchronizes the input and output clocks in 5 clock cycles but maintains one cycle dynamic locking. The WRADDLL reduces the clock skew between the input and output clocks with three innovative techniques. First, by improving the mirror control circuit, the WRADDLL operates correctly with a flexible duty cycle clock signal. Second, the WRADDLL works precisely and ignores the effect of output load changes by moving the measurement delay line beyond the output driver. Besides, it can achieve one-cycle dynamic locking. Finally, the WRADDLL utilizes the band selector to achieve wide-range operation. After fine tuning, the maximum static phase error is less than 3% of clock cycle. The chip is fabricated by 90 nm standard CMOS process. Its operating frequency range is from 200 MHz to 2 GHz. The power consumption and RMS jitter are 3.24 mW and 1.49 ps at 2 GHz, respectively. The active area of this chip is 0.011 mm2.
期刊介绍:
Analog Integrated Circuits and Signal Processing is an archival peer reviewed journal dedicated to the design and application of analog, radio frequency (RF), and mixed signal integrated circuits (ICs) as well as signal processing circuits and systems. It features both new research results and tutorial views and reflects the large volume of cutting-edge research activity in the worldwide field today.
A partial list of topics includes analog and mixed signal interface circuits and systems; analog and RFIC design; data converters; active-RC, switched-capacitor, and continuous-time integrated filters; mixed analog/digital VLSI systems; wireless radio transceivers; clock and data recovery circuits; and high speed optoelectronic circuits and systems.