Exploring Memory-Oriented Design Optimization of Edge-AI Hardware for Extended Reality Applications

IF 2.8 3区计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Micro Pub Date : 2023-11-01 DOI:10.1109/mm.2023.3321249

Vivek Parmar, Syed Shakib Sarwar, Ziyun Li, Hsien-Hsin S. Lee, Barbara De Salvo, Manan Suri

{"title":"Exploring Memory-Oriented Design Optimization of Edge-AI Hardware for Extended Reality Applications","authors":"Vivek Parmar, Syed Shakib Sarwar, Ziyun Li, Hsien-Hsin S. Lee, Barbara De Salvo, Manan Suri","doi":"10.1109/mm.2023.3321249","DOIUrl":null,"url":null,"abstract":"Low-Power Edge-AI capabilities are essential for on-device extended reality (XR) applications to support the vision of Metaverse. In this work, we investigate two representative XR workloads: (i) Hand detection and (ii) Eye segmentation, for hardware design space exploration. For both applications, we train deep neural networks and analyze the impact of quantization and hardware-specific bottlenecks. Through simulations, we evaluate a CPU and two systolic inference accelerator implementations. Next, we compare these hardware solutions with advanced technology nodes. The impact of integrating state-of-the-art emerging non-volatile memory (NVM) technology (STT/SOT/VGSOT MRAM) into the XR-AI inference pipeline is evaluated. We found that significant energy benefits (≥24%) can be achieved for hand detection (IPS=10) and eye segmentation (IPS=0.1) by introducing NVM in the memory hierarchy for designs at 7nm node while meeting minimum IPS (inference per second). Moreover, we can realize substantial reduction in area (≥30%) owing to the small form factor of MRAM.","PeriodicalId":13100,"journal":{"name":"IEEE Micro","volume":"51 12","pages":"0"},"PeriodicalIF":2.8000,"publicationDate":"2023-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Micro","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/mm.2023.3321249","RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}

引用次数: 0

Abstract

Low-Power Edge-AI capabilities are essential for on-device extended reality (XR) applications to support the vision of Metaverse. In this work, we investigate two representative XR workloads: (i) Hand detection and (ii) Eye segmentation, for hardware design space exploration. For both applications, we train deep neural networks and analyze the impact of quantization and hardware-specific bottlenecks. Through simulations, we evaluate a CPU and two systolic inference accelerator implementations. Next, we compare these hardware solutions with advanced technology nodes. The impact of integrating state-of-the-art emerging non-volatile memory (NVM) technology (STT/SOT/VGSOT MRAM) into the XR-AI inference pipeline is evaluated. We found that significant energy benefits (≥24%) can be achieved for hand detection (IPS=10) and eye segmentation (IPS=0.1) by introducing NVM in the memory hierarchy for designs at 7nm node while meeting minimum IPS (inference per second). Moreover, we can realize substantial reduction in area (≥30%) owing to the small form factor of MRAM.

查看原文本刊更多论文

面向扩展现实应用的边缘ai硬件面向内存设计优化研究

低功耗边缘ai功能对于设备上扩展现实(XR)应用程序支持Metaverse愿景至关重要。在这项工作中，我们研究了两个代表性的XR工作负载:(i)手检测和(ii)眼分割，用于硬件设计空间探索。对于这两种应用，我们都训练了深度神经网络，并分析了量化和特定硬件瓶颈的影响。通过仿真，我们评估了一个CPU和两个收缩推理加速器的实现。接下来，我们将这些硬件解决方案与先进的技术节点进行比较。评估了将最先进的新兴非易失性存储器(NVM)技术(STT/SOT/VGSOT MRAM)集成到XR-AI推理管道中的影响。我们发现，在满足最小IPS(每秒推理)的情况下，通过在7nm节点设计的内存层次结构中引入NVM，可以实现手部检测(IPS=10)和眼睛分割(IPS=0.1)的显著能量效益(≥24%)。此外，由于MRAM的小尺寸，我们可以实现面积的大幅减少(≥30%)。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

IEEE Micro 工程技术-计算机：软件工程

CiteScore

7.50

自引率

0.00%

发文量

164

审稿时长

>12 weeks

期刊介绍： IEEE Micro addresses users and designers of microprocessors and microprocessor systems, including managers, engineers, consultants, educators, and students involved with computers and peripherals, components and subassemblies, communications, instrumentation and control equipment, and guidance systems. Contributions should relate to the design, performance, or application of microprocessors and microcomputers. Tutorials, review papers, and discussions are also welcome. Sample topic areas include architecture, communications, data acquisition, control, hardware and software design/implementation, algorithms (including program listings), digital signal processing, microprocessor support hardware, operating systems, computer aided design, languages, application software, and development systems.