Electronics Hardware Chip Design for Router–Router Communication

Abstract

In contrast to scalar CPUs, end scaling refers to the use of heterogeneous multiprocessor systems-on-chip. Calculations made by an application consume less energy when it is run on the appropriate processor elements (PEs) that have been enhanced for difficult operations. However, as the PEs are increased, communication becomes more and more important. The on-chip interconnect technology of NoC uses scaled-down communication techniques from networks. A router is a physical or virtual device that acts as a shared form of gateway for material between two or more packet-switched processor networks. The router is used for NoC connection in SoC and concerned designs for router–router communication. This paper presents the hardware chip design of the 2D routers and employs router–router chip communication between two routers using independent chips and integrated NoC. The router hardware chip design is done in Xilinx Integrated System Environment (ISE) 14.7 software. Modelsim 10.0 is used for logic verification utilizing data packets sent from all input/output ports.