Iaçanã Ianiski Weber, Angelo Elias Dal Zotto, Fernando Gehm Moraes
{"title":"Chronos-v: a many-core high-level model with support for management techniques","authors":"Iaçanã Ianiski Weber, Angelo Elias Dal Zotto, Fernando Gehm Moraes","doi":"10.1007/s10470-023-02190-8","DOIUrl":null,"url":null,"abstract":"<div><p>This work presents <i>Chronos-V</i>, a Many-Core System-on-Chip (MCSoC) that adopts abstract hardware modeling, executing the FreeRTOS Operating System (OS) at each processing element (PE). <i>Chronos-V</i> is a heterogeneous architecture with two regions: (i) General Purpose Processing Elements (GPPE), responsible for executing user applications; (ii) peripherals that provide IO capabilities or hardware acceleration to the system. Besides the standard goal of high-level models, design space exploration at early design stages with reduced simulation time, our goal is to advance the state-of-the-art in the MCSoC research field by proposing an architecture with hardware and software support for management techniques. As a case study, we present an ODA (Observe-Decide-Actuate) loop for thermal management, comparing it to a dark silicon patterning mapping in a platform with 196 PEs. Thermal maps show the benefits of using dynamic thermal management regarding hotspot avoidance and temperature reduction.\n</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":null,"pages":null},"PeriodicalIF":1.2000,"publicationDate":"2023-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Analog Integrated Circuits and Signal Processing","FirstCategoryId":"5","ListUrlMain":"https://link.springer.com/article/10.1007/s10470-023-02190-8","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
This work presents Chronos-V, a Many-Core System-on-Chip (MCSoC) that adopts abstract hardware modeling, executing the FreeRTOS Operating System (OS) at each processing element (PE). Chronos-V is a heterogeneous architecture with two regions: (i) General Purpose Processing Elements (GPPE), responsible for executing user applications; (ii) peripherals that provide IO capabilities or hardware acceleration to the system. Besides the standard goal of high-level models, design space exploration at early design stages with reduced simulation time, our goal is to advance the state-of-the-art in the MCSoC research field by proposing an architecture with hardware and software support for management techniques. As a case study, we present an ODA (Observe-Decide-Actuate) loop for thermal management, comparing it to a dark silicon patterning mapping in a platform with 196 PEs. Thermal maps show the benefits of using dynamic thermal management regarding hotspot avoidance and temperature reduction.
期刊介绍:
Analog Integrated Circuits and Signal Processing is an archival peer reviewed journal dedicated to the design and application of analog, radio frequency (RF), and mixed signal integrated circuits (ICs) as well as signal processing circuits and systems. It features both new research results and tutorial views and reflects the large volume of cutting-edge research activity in the worldwide field today.
A partial list of topics includes analog and mixed signal interface circuits and systems; analog and RFIC design; data converters; active-RC, switched-capacitor, and continuous-time integrated filters; mixed analog/digital VLSI systems; wireless radio transceivers; clock and data recovery circuits; and high speed optoelectronic circuits and systems.