Electron Microscopy and Failure Analysis

Abstract

As VLSI technology moves in a direction toward more complex chips with increasingly smaller design rules, device failure analysts have been asked to produce microscope images of VLSI features with increasingly greater resolution. This has led to the increased use of the transmission electron microscope (TEM) as an integral part of process development/failure analysis efforts. The major obstacle to the use of the TEM has been the problem of sample preparation; satisfactory sample preparation methods have been developed, and these methods and the use of a TEM test pattern are described. Both the TEM and scanning electron microscope have other modes of operation (in addition to morphology study) that are relevant and in some cases essential to process development/failure analysis effort, and these are described: junction delineation, phase identification, chemical analysis, electrical mapping and microdefect analysis.