Hierarchical identification of NBTI-critical gates in nanoscale logic

Abstract

One of the main reliability concerns in the nanoscale logic is the time-dependent variation caused by Negative Bias Temperature Instability (NBTI). It increases the switching threshold voltage of pMOS transistors and as a result slows down signal propagation along the paths between flip-flops, thus causing functional failures in the circuit. In this paper we propose an approach to identify NBTI-critical gates in nanoscale logic. The method is based on static timing analysis that provides delay critical paths under NBTI-induced delay degradation. An analysis on these critical paths is performed in order to select the set of gates that have the highest influence on circuit aging. These gates are to be hardened against NBTI aging effects guaranteeing correct circuit behavior under the given timing and circuit lifetime constraints. The proposed approach is demonstrated on an industrial ALU circuit design.