Total dose performance of conventional static and dynamic circuits in a radhard 0.18-/spl mu/m FDSOI process

Abstract

Static and dynamic circuits were fabricated in the MIT-LL 0.18-/spl mu/m FDSOI CMOS process, and exhibited a high tolerance to total dose radiation up to 1 Mrad (SiO/sub 2/). Circuits were designed using conventional design rules and layout techniques, i.e., they are not radhard-by-design. Hardening was done at the circuit fabrication level using process enhancements. These are the first circuit-level hardness results reported to date for these new enhancements.