Characterization of the mechanical stress impact on device electrical performance in the CMOS and III–V HEMT/HBT heterogeneous integration environment

Abstract

The stress impact of the CMOS and III-V heterogeneous integration environment on device electrical performance is being characterized. Measurements from a partial heterogeneous integration fabrication run will be presented to provide insight into how the backside source vias, alternatively referred to as through-silicon-carbide vias (TSCVs), used within the heterogeneous integration environment impacts GaN HEMT device-level DC performance.