Multilevel interconnection for half-micron ULSI's

Abstract

In order to integrate half-micron experimental CMOS and BiCMOS LSIs, multilevel interconnection process technology utilizing relatively conventional techniques has been developed. Some design rules are 0.8- mu m metal line and 0.6- mu m space for the first and the second level. To achieve these requirements, dielectric planarization techniques were adopted. Heavily doped BPSG glass flow was used to cover underlying poly steps, and spin-on-glass planarization was used at the metal steps. Tungsten (W) was selected for the first-level wiring. Although the step coverage of the sputtered W film at the reflow tapered 0.6- mu m contact hole was poor, high current capability was observed due to the high electromigration immunity of W. At via holes, step coverage was slightly improved using shallow voltage bias sputtering of Al. Al/TiN layered metallization was used for the second to fourth-level wirings to maintain stress migration immunity. At the third and fourth levels, design rules were widened because of the focus depth.<>