NW-FET Modelling to be Integrated in a SET-FET Circuit

Abstract

In this work, an electrical study of a vertical nanowire (NW)-based Field Effect Transistor (FET) is presented. The resulting output current from the modelled NW-FET is optimized in terms of multiple parameters, in order to enhance the behavior at subthreshold regime. Variability tolerance is analyzed as well, in order to attain improvements concerning average device performance and stability. A process simulation model for a NW-FET is built in perspective for its further manufacturability and implementation into hybrid SET-FET circuits.