Step back to see more [transaction level SoC debugging and verification]

Abstract

The design, debug and verification of embedded system-on-chips (SoCs) produces a series of obstacles. Transfer level (RTL) simulation of large designs - a necessary part of the debug process - can generate tremendous amounts of signal-level data that the engineer must then track and analyse. Clearly, there is a need for a better debug and verification methodology. Most embedded SoC architects are really concerned with the transactions that result from software requests, such as the reads from and writes to memory. This article proposes that it is desirable to migrate to a higher level of abstraction that works at the transaction level. This abstraction level offers a viable high-utility complement to debugging with just RTL simulation data.