A study using two stage NBTI model for 32 nm high-k PMOSFET

Abstract

Kinetics of E'centers and threshold voltage shift, (ΔVth) of High-K Metal Gate Stacks has been comprehensively studied using two - stage Negative Bias Temperature Instability (NBTI) model. To effectively study the kinetics of E' centers, the two stage model was simulated with stage one only and then simulated in both stages. The evolution of trap kinetics was further investigated by varying parametric of energy barriers. We found that the model capable to explain the hole trapping and de-trapping mechanism occurs in NBTI degradation particularly on the transformation between hole traps into a more permanent form which explain the process of de-passivation of interface trap precursor as triggered by hole captured at an E' center precursor.