WSI architecture of a neurocomputer module

Abstract

Discusses application and technology related constraints on the implementation of neurocomputing systems on a wafer. The resulting neurocomputer architecture builds on the experience obtained with a 42 cm/sup 2/ soft-configured chip which carries a 2-dimensional array of multipliers in CMOS. The architecture is specially adapted to pattern recognition of video images by means of generalized multilayer-perceptrons.<>