Design consideration for SOI gate controlled hybrid transistor operating at low voltage

Abstract

The comprehensive design guidelines for SOI gate controlled hybrid transistor (GCHT) are provided in this paper for the first time, especially for GCHT operating at low voltage, which is an advantageous operating region of GCHT. The investigated mechanisms in this study involve short channel effects, current driving capability, device off-characteristics and open-circuit voltage gain. The design curves for low operating voltage are presented by synthesizing the results, with tradeoffs between different parameter requirements for different effects illustrated explicitly. The allowable design region is greatly-broadened, pointing out the direction for deep submicron device development.