Crosstalk-avoidance coding for low-power on-chip bus

Abstract

In this paper, a crosstalk-avoidance (CA) bus coding approach is developed to produce area-efficient, low-power codes for global data busses. Proposed codes are codes without memory using shielding boundary strategy. Related code generation algorithm is also developed. The probabilistic distribution of input data could be included to reduce the power consumption. The performance improvement of CA codes is nearly 2x for heavily coupled busses based on theoretical analysis. As compared to uncoded datawords, proposed codes show 16.1% to 21.5% power-reduction on bus for an equiprobable 32-bit bus design.