Enhanced Design Architecture to Suppress Leakage Current of High-Voltage (HV) Lateral nMOSFETs in 4H-SiC

Abstract

This paper demonstrates and presents an enhanced design architecture to suppress the leakage from the high-voltage (HV) lateral MOSFETs in 4H-SiC. The demonstrated MOSFETs were fabricated on an N-epi/P-epi/N+ substrate. A comparative analysis was conducted between the performance of the improved design architecture and the conventional architecture, and the outcomes exhibit a notable decrease in the magnitude of the leakage current. The proposed device architecture possesses the capability to effectively fulfill the design specifications of a durable lateral power MOSFET to be used in silicon carbide (SiC) power integrated circuits (ICs).