Simulated Annealing Method for Construction of High-Girth QC-LDPC Codes

Abstract

We present a simulated annealing method that construct high-girth quasi-cyclic low-density parity check (QC-LDPC) codes. The proposed method is applicable to both regular and irregular protograph codes. The method show improvement in term of minimal circulant size compare with previous described methods: Hill-Climbing and improved PEG. Simulated results are presented to demonstrate performance gain of proposed construction method in error-floor region under base graph 2 (BG2) using 5G eMBB standard length adaption method.