Power Envelope Analysis for the Thermal Optimization of a Chiplet Module

Abstract

In this paper, the thermal performances of a Chiplet module with different numbers of dies were studied. The Chiplet module was assumed to be placed in the same server system, with the same ambient condition, and using the same heat sink. A thermal simulation was conducted to obtain the junction temperatures of dies using different power magnitudes. With the change of power magnitudes of the dies, a thermal resistor matrix was calculated. Finally, with the calculation of the thermal resistor matrix, a unique power envelope plot was developed to determine if the power magnitudes of the chips on the Chiplet module caused any reliability concern. A risk factor was calculated to determine if the power magnitude of the die is within the safe region. With risk factors, we will be able to quantify the differences of applied powers with respect to the maximum allowed limits. We have expanded the usage of the power envelope plots to the Chiplet modules having more than three dies. The power envelope plots are a good tool for designers to optimize the power magnitudes, especially at the early stage of the Chiplet module design.