Stress tests [reusable design verification components]

Abstract

Reusable verification components provide a way of streamlining the process of checking not just logic blocks but protocol stacks and system designs. Used in combination with other techniques, they can provide a way of stressing the system to reveal bugs other approaches would not find. Building reusable devices for verification is becoming a must in order to reduce the verification overhead for designs. However, it is no longer enough to simply build a device which can only attach to a design under test (DUT) or bus and operate in a single way Instead, verification components (VCs) are becoming more common. Such devices provide a reusable way of testing devices with a common functionality or common protocol. However, it is also becoming necessary to be able to reuse what have traditionally been block-level verification devices at the system level.