System design considerations for FPGA synthesis

Abstract

This article provides an overview of some of the system level considerations when designing with FPGA/CPLD devices. The tools supporting these types of designs vary widely in the features that have a significant impact on the time and effort it takes to complete a design. With flexibility as the key, you should ensure your tools support a "top-down design" approach, have mixed mode (language and schematic) entry, and are integrated into a tool which can provide timing simulation and board layout. Finally, you should realize that CPLD devices now have a unique combination of speed and density that can potentially be used in areas where only FPGAs were considered viable.<>