RTL delay macro-modeling with Vt and Vdd variability

Abstract

Recent low-power design utilizes a variety of approaches for Vdd and Vt control to reduce dynamic and leakage power. It is important to be able to explore various low-power design options at a high-level early in the design process. Furthermore, process variation is becoming large and greatly affects the power and delay results. In particular, the delay analysis becomes very complicated and time-consuming with existing tools. This paper proposes a new efficient RTL delay macro-model to address these recent problems. The goal is to provide transistor-level accuracy at the RTL level with Vt and Vdd variability. It also includes the ability to handle PVT variations. The validation of the model is demonstrated by comparison with a circuit simulator and a timing verification tool. The experiments show this macro-model predicts the delay for variable Vdd and Vt with an accuracy of ±5% against HSPICE™ and ±10% against PrimeTime™ for a number of ITC'99 benchmark circuits.