Materials, Processes, and Markets for Monolithic III-V Devices in Silicon Integrated Circuits

Abstract

Materials and processes to create monolithic 111-V+CMOS circuits have been developed iteratively with inputs from potential market application needs and semiconductor industry infrastructure. The GaN LED and III-V HEMT platforms are earliest to develop and driven by currently anticipated market needs. The developed process flow involves conventional 200mm CMOS front-end processing in a CMOS foundry, merging the CMOS wafer with a III-V/Si wafer, processing III-V devices in a silicon fabrication environment, and final interconnection via returning the wafer to a CMOS foundry for back-end interconnection. III-V+CMOS silicon ICs are designed in a Cadence environment using foundry PDKs modified with insertion of the integrated III-V device models. The overall method described above is invariant for the different III-V's that are integrated into silicon ICs. Circuits have been designed using GaN LED+CMOS, GaN HEMT+CMOS, InGaAs HEMT+CMOS, and InGaP LED+CMOS platforms.