Embedded Parallel Systolic architecture for multi-filtering techniques using FPGA

Abstract

Computing systems typically suffer from delay in data processing. This delay is caused by computational power, architecture of the processor unit, synchronization signals, and so on. To enhance the performance of these systems by increasing the processing power, a new architecture and clocking technique is carried out in this paper. This new architecture design called Embedded Parallel Systolic Filters (EPSF) that can process data gathered from sensors and landmarks are proposed in our study using a high-density reconfigurable device (FPGA chip). The results show that EPSF architecture and bit-flag with a flicker clock perform significantly better in multiple input sensors signals under both continuous and interrupted conditions. Unlike the usual processing units in previous tracking and navigation systems used in robots, this system allows autonomous control of the robot through a multiple technique of filtering and processing. Furthermore, it provides fast performance and a minimal size for the entire system that minimizing the delay about 70%.