{"title":"DISC: dynamic instruction stream computer","authors":"M. Nemirovsky, F. Brewer, R. Wood","doi":"10.1145/123465.123498","DOIUrl":null,"url":null,"abstract":"The Dynamic Instruction Stream Computer is a novel computer architecture which addresses many of the problems present in real-time systems. The DISC operates by allowing multiple instruction streams (ISs), representing different processes to run concurrently by instruction interleaving on the pipeline. Also, the throughput of the DISC can be partitioned in any way between the multiple ISs. Conventional architectures are more concerned with overall performance and throughput than with real-time response. In other words, they optimize the system to the functions that are more heavily used without regard to responsiveness to individual requests. Applications abound where a high degree of responsiveness is required, without too much sacrifice of overall efficiency. This is particularly true in real-time control applications where it is important to optimize the critical loops and respond promptly to interrupts. DISC addresses this problem by dynamically partitioning the processor throughput between multiple instruction streams based upon requirement demands. In this way different tasks and interrupt priorities can be assigned to guarantee their deadlines.","PeriodicalId":118572,"journal":{"name":"MICRO 24","volume":"87 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"28","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"MICRO 24","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/123465.123498","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 28
Abstract
The Dynamic Instruction Stream Computer is a novel computer architecture which addresses many of the problems present in real-time systems. The DISC operates by allowing multiple instruction streams (ISs), representing different processes to run concurrently by instruction interleaving on the pipeline. Also, the throughput of the DISC can be partitioned in any way between the multiple ISs. Conventional architectures are more concerned with overall performance and throughput than with real-time response. In other words, they optimize the system to the functions that are more heavily used without regard to responsiveness to individual requests. Applications abound where a high degree of responsiveness is required, without too much sacrifice of overall efficiency. This is particularly true in real-time control applications where it is important to optimize the critical loops and respond promptly to interrupts. DISC addresses this problem by dynamically partitioning the processor throughput between multiple instruction streams based upon requirement demands. In this way different tasks and interrupt priorities can be assigned to guarantee their deadlines.