{"title":"Cost-effective implementation of ITU-T G.723.1 on a DSP chip","authors":"Sang-Min Lee, Sang-il Park, Y. Jang","doi":"10.1109/ISCE.1997.658344","DOIUrl":null,"url":null,"abstract":"This paper presents a full-duplex, real-time implementation of ITU-T G.723.1 speech coder using the SSP1820, Samsung's DSP chip which is based on a 16-bit fixed-point Oak core. Optimization methods are proposed in order to reduce the total cycle time consumed in real-time implementation. The multi-pulse maximum likelihood quantization (MP-MLQ) excitation search block which is the most computation-intensive block in the coder is restructured to reduce the algorithmic redundancy. In addition, efficient filtering methods and memory management are utilized for further optimization. The bit-exact verification with the ITU test vectors and performance evaluation aspects are also discussed in this paper.","PeriodicalId":393861,"journal":{"name":"ISCE '97. Proceedings of 1997 IEEE International Symposium on Consumer Electronics (Cat. No.97TH8348)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1997-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ISCE '97. Proceedings of 1997 IEEE International Symposium on Consumer Electronics (Cat. No.97TH8348)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCE.1997.658344","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
This paper presents a full-duplex, real-time implementation of ITU-T G.723.1 speech coder using the SSP1820, Samsung's DSP chip which is based on a 16-bit fixed-point Oak core. Optimization methods are proposed in order to reduce the total cycle time consumed in real-time implementation. The multi-pulse maximum likelihood quantization (MP-MLQ) excitation search block which is the most computation-intensive block in the coder is restructured to reduce the algorithmic redundancy. In addition, efficient filtering methods and memory management are utilized for further optimization. The bit-exact verification with the ITU test vectors and performance evaluation aspects are also discussed in this paper.