A CMOS gate array with dynamic-termination GTL I/O circuits

Abstract

A 530 kG gate array with novel GTL I/O circuits has been developed using 0.5 /spl mu/m CMOS triple-metal-layer process technology. The I/O circuit of a push-pull output driver and a dynamic termination receiver can transmit 250 Mb/s data through a long stub line which is connected to a terminated bus line. IDDQ testability is designed for the differential receiver without any delay time overheads.