Circuit design of a 9ns-HIT-delay 32K byte cache macro

Abstract

Introduction After a Reduced Insrmction Set Computer (RISCJ was shown to be effective in increasing CPU perfomnceIl1, s e v d attempls have teen made to funher improve the CPU performance by including cache memory an the same chipl21. However, the formerly reported cache size is limited up to 2K bym. which is not sufficient to obtain more than 95% hit rate. This paper describes a 32K byte cache macro with an erperimmml RISC implemented on the Same chip.