High-performance, low-power skewed static logic in very deep-submicron (VDSM) technology

Abstract

This paper presents S/sup 2/L, which exhibits low-power, high-speed with use of positive feedback circuits and dual Vt. Topology-dependent dual Vt approach suppresses leakage current while boosting the performance in VDSM technology. S/sup 2/L consumes less dynamic and static power compared to Monotonic Static (MS) CMOS. We present simulation results of NAND-NOR gate chains and 32-b adders to demonstrate the effectiveness of the S/sup 2/L compared to other techniques. Design automation for the proposed circuit architecture can be achieved easily due to cascading flexibility.