62-GHz 24-mW static SiGe frequency divider

H. Knapp, M. Wurzer, K. Aufinger, J. Bock, T. Meister
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引用次数: 4

Abstract

We present a static frequency divider with a divide ratio of 16. The circuit is realized in current-mode logic (CML) and operates up to a maximum frequency of 62 GHz. The first master-slave flip-flop uses shunt peaking and consumes only 4 mW from a 2 V supply. The total supply current including all four divider stages and buffers is 12 mA. The circuit is manufactured in a 200-GHz f/sub T/ SiGe bipolar process.
62-GHz 24mw静态SiGe分频器
提出了一种分频比为16的静态分频器。该电路采用电流模式逻辑(CML)实现,工作频率最高可达62 GHz。第一个主从触发器使用分流调峰,从2v电源只消耗4mw。包括所有四个分压器级和缓冲器在内的总电源电流为12毫安。该电路采用200 ghz f/sub T/ SiGe双极工艺制造。
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