H. Knapp, M. Wurzer, K. Aufinger, J. Bock, T. Meister
{"title":"62-GHz 24-mW static SiGe frequency divider","authors":"H. Knapp, M. Wurzer, K. Aufinger, J. Bock, T. Meister","doi":"10.1109/SMIC.2004.1398153","DOIUrl":null,"url":null,"abstract":"We present a static frequency divider with a divide ratio of 16. The circuit is realized in current-mode logic (CML) and operates up to a maximum frequency of 62 GHz. The first master-slave flip-flop uses shunt peaking and consumes only 4 mW from a 2 V supply. The total supply current including all four divider stages and buffers is 12 mA. The circuit is manufactured in a 200-GHz f/sub T/ SiGe bipolar process.","PeriodicalId":288561,"journal":{"name":"Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.","volume":"44 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMIC.2004.1398153","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
We present a static frequency divider with a divide ratio of 16. The circuit is realized in current-mode logic (CML) and operates up to a maximum frequency of 62 GHz. The first master-slave flip-flop uses shunt peaking and consumes only 4 mW from a 2 V supply. The total supply current including all four divider stages and buffers is 12 mA. The circuit is manufactured in a 200-GHz f/sub T/ SiGe bipolar process.