A thermal distribution, lifetime reliability prediction and spare TSV insertion platform for stacking 3D-ICs

Abstract

Thermal dissipation is one of the most critical challenges for stacking 3D-ICs, where the heat cannot easily transfer through several layers of silicon. As the Mean Time to Failure (MTTF) decreases exponentially with the operating temperature as in Black’s mode [1], stacking 3D-ICs also confront the reliability threat. Notably, Copper has a higher activation energy than CMOS, which makes Copper Through-Silicon-Vias vulnerable with the thermal-accelerated failure. Therefore, this paper presents a platform where we investigate the thermal distribution, predict the reliability, and propose a method for efficiently insert spare TSVs to ensure lifetime reliability. To demonstrate our platform, we apply a TSV-based 3D-NoC (3D Network-on-Chip) under the PARSEC benchmarks. We also illustrate the thermal-aware TSV redundancies insertion using grid search and genetic algorithm to balance the number of TSVs and the target MTTF.