Modeling layout, distribution and breakdown effects in GaN HEMTs in the MVSG approach

Abstract

In this work, we extend the industry standard MIT Virtual Source GaN HEMT (MVSG) model to include layout dependent effects such as scaling of parasitic fringing capacitances, scaling of distributed gate- and channel-resistance, and scaling of thermal network, which target wide-periphery FETs for high-frequency (HF) power amplification applications. Further, we capture the safe-operating area (SOA) of the device by including channel-breakdown in addition to gate-diode breakdown which is useful for high voltage (HV) applications. The modeling approach satisfies Gummel symmetry-benchmarks and is valid for symmetric switch FETs.