Implementation of Modular Subtraction Unit for NTT-based Polynomial Multiplier

Abstract

This paper suggests the efficient implementation of Modular Subtraction Unit for NTT-based polynomial multiplier on ASIC design. We will introduce the basic algorithms of Number Theoretic Transform (NTT) and the Modular Arithmetic briefly, compare the implementation of the modular subtraction unit with the one which suggested in [1] by intuitive way. We reduced about 30% transistors in 17-bit Modular Subtraction Unit.