Single-chip tunable heterodyne notch filters implemented in FPGA's

Abstract

Two single-chip designs implement in FPGA's a high-order tunable IIR notch filter using a new digital heterodyne technique. The notch center frequency can be tuned from DC to the Nyquist frequency and the characteristics of the IIR generated notch filter can be re-programmed for specific applications. The first chip is a single-chip version of a filter previously designed using three Xilinx FPGA's. Through Multiplexing and Pipelining it is possible to implement all three chips on one FPGA. The second chip makes use of a reduction in the sin-cos look-up tables to reduce the hardware even more. Both chips offer very flexible adaptive notch filters with the ability to design, a very complex notch without complicating the tuning process. These new single-chip versions offer considerable power and cost advantages over the earlier three-chip version.