A buffer cache architecture for smartphones with hybrid DRAM/PCM memory

Abstract

Flash memory is widely used in mobile phones to store contact information, applications files and other types of data. In an operating system, the buffer cache keeps the I/O blocks in DRAM to reduce the slow flash accesses. However, in smartphones, the benefits of buffer cache are reduced due to the bulk of synchronous writes of applications for reliability issues. In this paper, we propose a buffer cache architecture with hybrid DRAM/PCM memory, which improves the I/O performance for smartphones. We use a DRAM first-level buffer cache to provide high buffer cache performance and a PCM last-level buffer cache to reduce the impact of frequent synchronous writes. Based on the proposed hierarchical buffer cache architecture, we propose a sub-dirty-block management and background flush to reduce the impact of the PCM write limitation and the dirty block writeback overhead, respectively. The experimental results show that with the proposed mechanisms, our hierarchical buffer cache can improve the I/O response time by 20% compared to the conventional buffer cache.