{"title":"Revisiting Smalltalk-80 blocks: a logic generator for FPGAs","authors":"B. Pottier, J. Llopis","doi":"10.1109/FPGA.1996.564744","DOIUrl":null,"url":null,"abstract":"A Smalltalk-80 block is an encapsulation of code the evaluation of which is delayed, either for casual or repetitive execution (message value), or for process creation (message fork). Execution is driven following the object oriented paradigm with late binding of messages to actual functions. A logic generator is described, which is based on the compilation of blocks to logic specifications. The translation process applies the block to a collection of objects representing a definition set. Resulting and original object collections are then translated into binary logic depending on observed classes. Block reference to remote variables allows sequential circuit implementations. The logic generator operates in an interactive environment supporting BLIF and XNF logic representations. Logic optimization and partitioning is achieved using the SIS package. The testbed is the ArMen parallel computer which includes an FPGA ring.","PeriodicalId":244873,"journal":{"name":"1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines","volume":"497 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/FPGA.1996.564744","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
Abstract
A Smalltalk-80 block is an encapsulation of code the evaluation of which is delayed, either for casual or repetitive execution (message value), or for process creation (message fork). Execution is driven following the object oriented paradigm with late binding of messages to actual functions. A logic generator is described, which is based on the compilation of blocks to logic specifications. The translation process applies the block to a collection of objects representing a definition set. Resulting and original object collections are then translated into binary logic depending on observed classes. Block reference to remote variables allows sequential circuit implementations. The logic generator operates in an interactive environment supporting BLIF and XNF logic representations. Logic optimization and partitioning is achieved using the SIS package. The testbed is the ArMen parallel computer which includes an FPGA ring.