Yield enhancement architecture of WSI cube-connected cycle

Abstract

The current state of the art in VLSI technology has stimulated research in parallel computers which satisfy the continued increasing demand for computing power in the fields of advanced science and technology. The cube-connected cycle (CCC) is one of the most attractive interconnections and architectures for parallel computers. This paper addresses a new yield enhancement architecture of the cube-connected cycle implemented on a silicon wafer in (WSI), which is expected as a promising technology to construct parallel computers on silicon wafers. The performance of the proposed architecture is discussed with respect to yields of system. It is confirmed by comparing with previous work that the reconfigurable architecture based on the row-column redundant scheme achieves better yield enhancement than earlier designs.<>