RTL to GDSII Flow Implementation of 8-bit Baugh-Wooley Multiplier

Abstract

In this paper, the implementation of the Baugh-Wooley multiplier for 8-bit signed multiplication is performed from RTL to GDSII generation to incorporate the physical design (PD) flow. Firstly, the RTL file is generated using the Verilog implementation of an 8-bit signed Baugh-Wooley multiplier and this RTL file is used while going through PD flow. For RTL to GDSII flow the open-source EDA tools are used for different intermediate levels such as synthesis, placement, routing, and timing analysis. Profuse results like power, area, timing constraints, layout, and frequency are incorporated and compared between the two technology nodes: 180 nm and 45 nm. In addition to this, the results of Baugh-Wooley multiplier are quantified with Booth Multiplier. By incorporating both the multipliers, it is seen that the Baugh-Wooley multiplier requires 36.68 % less area than the Booth multiplier and hence it is area efficient. However, it requires 44.60 % more power and 60 % more delay. The Baugh-Wooley multiplier is preferred if area is concerned with better slack, while Booth Multiplier can be preferred if power is concerned. In this paper, the proposed Baugh-Wooley multiplier delay and power constraints are also compared with other works.