High-speed implementation of JBIG arithmetic coder

Abstract

A high-speed architecture of the JBIG arithmetic coder is devised, which is dedicated to digital copying systems. Since the JBIG algorithm has a complicated procedure, it is hard to exploit pipeline and parallel facilities. This paper settles the issue arising in a pipelined architecture by employing a modified probability estimation table (MPET) and realizes a high speed architecture. In addition, the division of critical computations into two stages also contributes to achieving high speed coding. The proposed architecture of the JBIG arithmetic coder and decoder is synthesized from a Verilog description by using a 0.35 /spl mu/m CMOS library, and is compared with the conventional architecture. As a result the critical path delay of the proposed architecture has been reduced by 60%.