C. Hanna, D. Gillies, E. Cochon, A. Dorner, J. Alred, M. Hinkle
{"title":"DEMULTIPLEXER IC FOR MPEG2 TRANSPORT STREAMS","authors":"C. Hanna, D. Gillies, E. Cochon, A. Dorner, J. Alred, M. Hinkle","doi":"10.1109/ICCE.1995.517975","DOIUrl":null,"url":null,"abstract":"The MPEG2 systems was adopted as an international standard that specifies the multiplexed structure for combining audio and video data and a means of representing the timing information needed to replay synchronized sequences in real-time. This paper describes an integrated circuit developed to demultiplex desired programmes carried in an MPEG2 compatible transport stream. Up to nine simultaneous PIDs (packet identifiers) can be processed by the IC. The The MPEG2 demultiplexer is a fully static CMOS integrated circuit realized as an 0.8 /spl mu/m gate array. >","PeriodicalId":306595,"journal":{"name":"Proceedings of International Conference on Consumer Electronics","volume":"153 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of International Conference on Consumer Electronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCE.1995.517975","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
The MPEG2 systems was adopted as an international standard that specifies the multiplexed structure for combining audio and video data and a means of representing the timing information needed to replay synchronized sequences in real-time. This paper describes an integrated circuit developed to demultiplex desired programmes carried in an MPEG2 compatible transport stream. Up to nine simultaneous PIDs (packet identifiers) can be processed by the IC. The The MPEG2 demultiplexer is a fully static CMOS integrated circuit realized as an 0.8 /spl mu/m gate array. >