A 30.6-41.5uW 10-bit Column Parallel Single-Slope ADC with Minimum Voltage Feedback for CMOS Image Sensors

Abstract

A low power column parallel single-slope (SS) ADC with minimum voltage feedback (MVF) for CMOS image sensors is proposed. It utilizes a minimum voltage feedback approach and a dynamic bias structure to reduce the useless power consumption after the ramp signal passes the minimum voltage of a row. A 10-bit SS ADC with MVF was designed in a 180nm CMOS process. The simulated DNL and INL of the ADC are +0.124/-0.126 LSB and +0.1/-0.104 LSB, respectively. The SNDR is 61.29dB, the SFDR is 77.24dB and the ENOB is 9.89bit. The column power consumption of the ADC is 30.6-41.5uW at the frequency of 50 MHz and the power supply of 3.3V/1.8V. The column parallel comparator and the ramp generator using this technology in the ADC can reduce power consumption by up to 53.2% and 57.0%, respectively. The power consumption of the added MVF circuit is only 0.16uW/column.