Screening ICs On The Bare Chip Level: Temporary Packaging

Abstract

Several different temporary packaging concepts for integrated circuits (ICs) for pretest at speed and burn-in are introduced. Temporary packaging is achieved using standard labor and equipment resources already employed in permanent packaging. Experiments were carried out to validate the pretest process, and results are presented for the various materials used in the pretest process. The preferred method for temporary packaging along with the selected materials used is presented. Temporary packaging of integrated circuits for pretest with reasonable yield is demonstrated as feasible. >