Evaluation of the SEU Faults Coverage of a Simple Fault Model for Application-Oriented FPGA Testing

Abstract

Testing of FPGA-based designs persists to be a challenging task because of the complex FPGA architecture with heterogeneous components, and therefore a complicated fault model. The standard stuck-at fault model has been found insufficient. On the other hand, very precise FPGA fault models have been recently devised. However, these models are often excessively complex and require a lot of resources (run-time, memory) to manipulate with. In this paper, we propose a simple yet efficient combined fault model comprising bit-flips in look-up tables and stuck-at faults in the rest of logic. On top of this model, a dedicated SAT-based application-oriented ATPG has been designed. The main contribution of this paper is the evaluation of efficiency of the fault model with the respective ATPG by exhaustive hardware emulation of all possible SEUs in the configuration memory that may influence the functionality of the circuit implemented in the FPGA. We show that the obtained fault coverage reaches up to more than 99%, which makes the method applicable in practice. Even though combinational circuits are assumed only, the method can be used to quickly test safety-critical combinational cores.