Product reliability and maximum voltage limits from extrinsic gate oxide voltage ramp data

Abstract

The failure rate methodology applied previously to TDDB constant voltage data is extended to VRAMP data, to obtain the failure rate for a given supply voltage and gate oxide area or conversely, the maximum supply voltage for a given failure rate. The maximum voltage limit for sub-circuits occupying a small fraction of the chip area can also be determined. The methodology relies on the effective-oxide-thickness model and the unified TDDB model, where the E-model dominates at low fields and the 1/E-model dominates at high field.