{"title":"Automatic integration of hardware descriptions into system-level models","authors":"Ralph Görgen, Jan-Hendrik Oetjens, W. Nebel","doi":"10.1109/DDECS.2012.6219034","DOIUrl":null,"url":null,"abstract":"In this paper, we present a flow for integrating hardware descriptions into Simulink simulations. It enables the automatic generation of a Simulink component out of a hardware component model given as RT level VHDL. The approach is based on two steps. The first step transforms the VHDL model to SystemC. In contrast to existing VHDL-to-SystemC transformation tools, the readability and configurability of the input model is preserved. In addition, our approach yields a more exact model, as a custom designed VHDL-like data-type system is employed. The second step generates a specific wrapper to allow the use of the component in a Simulink simulation. This transformation strategy will be evaluated with two industrial automotive electronics hardware designs.","PeriodicalId":131623,"journal":{"name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DDECS.2012.6219034","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
In this paper, we present a flow for integrating hardware descriptions into Simulink simulations. It enables the automatic generation of a Simulink component out of a hardware component model given as RT level VHDL. The approach is based on two steps. The first step transforms the VHDL model to SystemC. In contrast to existing VHDL-to-SystemC transformation tools, the readability and configurability of the input model is preserved. In addition, our approach yields a more exact model, as a custom designed VHDL-like data-type system is employed. The second step generates a specific wrapper to allow the use of the component in a Simulink simulation. This transformation strategy will be evaluated with two industrial automotive electronics hardware designs.