Superconducting fault current limiter to mitigate the effect of DC line fault in VSC-HVDC system

Abstract

Voltage source converter based HVDC systems involving overhead transmission lines are prone to severe over-voltages during line faults. At present, they find applications only in back to back and/or underground cable transmission, with low power ratings. A conventional HVDC system suppresses the dc fault very well with the controllers and smoothing reactors while the same is not true with voltage source converter based HVDC systems. This necessitates the operation of some kind of protective devices. A superconducting fault current limiter, in this regard, is a possible device which can mitigate the effects of dc line faults. In this work, it is aimed to evaluate the dynamic performance of VSC-HVDC system integrated with a superconducting fault current limiter. The resistive superconducting fault current limiter is modeled in MATLAB and is interfaced with low voltage VSC-HVDC system, in PSCAD/EMTDC environment. The results of analysis for various ac and dc fault conditions are presented.