Design and Performance Analysis of a High Speed MAC Using Different Multipliers

Abstract

The multiply and Accumulate unit consists of a multiplier unit for multiplication and the product of multiplier is added up with previous result by using an adder. The result of a MAC unit is stored in an Accumulator. MAC is one of the part of digital processing systems. By reducing the delay of multiplier and adder, the overall delay of MAC unit can be reduced. In this paper the MAC unit is designed using different multipliers and adders. The comparative study of different multipliers and adders has been shown. The multipliers used were Vedic multiplier (based on Urdhava Tiryagbhyam sutra) and Wallace tree multiplier. The adders used were Kogge stone adder and Carry look ahead adder. The efficiency of MAC is observed through reduced delay and lesser hardware complexity. The synthesis and simulation was done by Xilinx software and ISim simulator.